Field
Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to vertically stacked system in package (SiP) structures and methods of fabrication.
Background Information
The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. As a result, various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices.
There are many different possibilities for arranging multiple die in an SiP. For example, vertical integration of die in SiP structures has evolved into 2.5D solutions and 3D solutions. In 2.5D solutions the multiple die may be flip chip bonded on an interposer that includes through vias as well as fan out wiring. In 3D solutions multiple die may be stacked on top of one another on an SiP substrate, and connected with off-chip wire bonds or solder bumps.
In one implementation, a memory die or package (e.g., dynamic random-access memory (DRAM)) is stacked on top of a logic die or package (e.g., application-specific integrated circuit (ASIC)) or system on chip (SoC). As the market for portable and mobile electronic devices advances larger memory capability is required of the memory die or package.